Fields

Materials & silicon

Curvature-native compute substrates and the physics of doing more with less.

substrateopen-PDK · Sky130
thesisgeometry is a material property
postureanalog and root-of-trust live inside the same fabric as compute
top-metal · global routing intermediate-metal · block I/O local-metal · within-block poly · device gates diffusion · active regions substrate · bulk silicon locality · 6×6 cell window root-of-trust
cross-section · locality inset · trust rings — one fabric, three guarantees
The science behind the silicon

Geometry is a material property

Our materials-and-silicon program studies how the geometry of a substrate constrains the cognition it can support. The work spans analog block design, layout that respects locality, and a security drop-in that puts the root of trust inside the same fabric as compute.

conventional view

geometry is a constraint imposed by the foundry that the architect spends effort fighting against.

our view

geometry is part of the cognitive substrate — when layout, analog references, and root-of-trust share the same organising principle, locality and energy are free.

Three lines of inquiry

Where the science sits

MS1

Curvature-native layout

Floor plans organised around the geometric primitives the cognitive substrate uses.

grid-aligned curvature-native
rewards floor plans built around the geometric primitives the substrate uses punishes rectangular layout that fights the cognitive primitives
MS2

Analog references

Bandgap, PTAT, and sense paths designed against the cognitive primitives, not retrofitted to fit them.

1.205 V 1.195 V −40 °C +125 °C target 1.20 V
rewards references designed against the cognitive primitives punishes analog retrofitted to fit digital after the fact
MS3

Hardware root of trust

Sealed storage, lockout, and post-quantum signing live inside the chip, not bolted on after the fact.

audit signing-path key-store root-of-trust
rewards trust primitives that share the fabric with compute punishes security bolted on after tape-out
analog block status

Four references, four stages

The analog corner of the substrate is small but load-bearing. We track each block by its honest status — IP-grade, SPICE-validated, in design, or in layout.

A1 IP

bandgap

reference voltage, temperature-invariant target

A2 SPICE

PTAT

proportional-to-absolute-temperature current source

A3 design

sense-amp

low-offset comparator on the cognitive sense path

A4 in-progress

PTAT layout

matched-pair layout under symmetry constraints

trust drop-in

Inside the fabric, not bolted on

Sealed storage, lockout, and post-quantum signing live alongside compute — the same die, the same provenance, the same audit.

  • TPM inside-fabric trusted-platform core
  • secmem secure-memory partition, separate read path
  • sealed sealed storage bound to die identity
  • BCH error-correcting layer for one-time keys
  • Shamir split-secret recovery primitive
  • audit append-only, tamper-evident event log
  • lockout rate-limited retry policy in hardware
  • PKCS#11 post-quantum signing surface (ML-DSA-class)

What is differentiating

The differentiating bet is that the substrate and the silicon share an organising principle. Where they do, the system gets locality and energy for free, because the physics is already doing the work the abstraction would otherwise have to enforce.

cross-cuts

The substrate ships with cognition, analog, and trust as one fabric

Where each lives in its own discipline elsewhere, we ship them as parts of the same material. The engineering surface is at geometry-native; the cognitive substrate is at cognition & memory.