G1 Layout
Floor-plans organised around the locality patterns the substrate already prefers.
Blocks that talk to each other sit next to each other. The wire length budget is paid where it matters; the rest pays nothing.
Geometry-native compute
Silicon where physics already does some of the work.
Silicon where the physics and the geometry of cognition are designed together.
controller GDS closed DRC 0 LVS clean PQ signing wallet
The thesis
Physics that already does the right thing
Compute is geometry: how charge moves, how signals route, how locality is enforced. Most chips treat that geometry as constraint. We treat it as substrate. Geometry-native compute means designing silicon whose layout, analog blocks, and signal paths share the primitives our cognitive substrate uses, so the physics is already doing some of the work.
most chips → geometry is a constraint to fight
ours → geometry is the substrate to lean into
How we get there
Three places the geometry shows up
G2 Analog blocks
References and sense paths designed against the cognitive primitives, not the other way around.
Bandgap, PTAT, and the sense path are tuned to the substrate, not retrofitted to it. The reference is part of the model, not a tolerance.
G3 Security
Root-of-trust, sealed storage, and post-quantum signing live inside the same fabric as compute.
TPM + secure memory + sealed storage + BCH + Shamir + audit log + lockout + wallet-backed ML-DSA signing — drop-in surface, not bolt-on.
Run 11 · cns_ctrl_top
The controller closed on a real foundry process.
Numbers below are measured from the GDS, not from a planning slide. They are the only scoreboard a tape-out has.
101,000
Cells placed
Phase 6.A2 control top
0
DRC violations
foundry rule deck clean
clean
LVS status
schematic ↔ layout matched
Sky130
Process node
open-PDK reference flow
Security · drop-in surface
Root-of-trust in the same fabric as compute.
A drop-in bundle, not a bolt-on. Ten components shipped together, with a wallet-backed post-quantum signing surface and an analog NTT study at the bottom.
01 TPM core shipped
02 secure memory core shipped
03 sealed storage core shipped
04 BCH codes error shipped
05 Shamir split shipped
06 audit log observ shipped
07 lockout policy shipped
08 PKCS#11 ML-DSA PQ sign wallet-backed
09 RTL skeleton fabric present
10 analog NTT fabric study
Progress
How the geometry program got to silicon
- 01Year 1
Thermal-ratchet emulator working
A functional substrate for adaptive compute with the full developmental stack on top.
- 02Year 2
Analog block bring-up
Bandgap IP closed; PTAT verified in SPICE; sense-amp and PTAT layout in active iteration.
- 03Year 2
Security drop-in shipped
TPM, secure memory, sealed storage, BCH, Shamir, audit log, lockout, and a wallet-backed post-quantum signing surface, with an RTL skeleton and an analog NTT study.
- 04Year 3
Controller GDS closed
Phase-6.A2 control top-level block closed on a foundry process. 101k cells, zero DRC, LVS clean.
What is differentiating
The differentiating bet is that the substrate and the silicon should share an organising principle. Where they do, the system gets locality and energy for free, because the physics is already doing the work the abstraction would otherwise have to enforce.