Obsidian 1.0 — Thermal-ratchet emulator
A research substrate exploring how adaptive compute can be driven by non-equilibrium dynamics. The whole developmental stack — from genome through production — sits on top of it.
Substrate · Tapeout
Silicon shaped like the
cognition it runs.
A curvature-native silicon family for substrate-aligned compute.
- Process
- Foundry tapeout
- Block
- cns_ctrl_top
- Run
- Phase-6.A2 · Run 11
- Status
- GDS closed
What Obsidian is
Silicon shaped like the cognition it runs
Obsidian is a family of chips, not a single product. Each generation explores a different relationship between physics and computation: thermal-ratchet dynamics for adaptive compute in the first generation, a curvature-native architecture in the second. The constant across the family is that the geometry of the cognitive substrate and the geometry of the silicon are designed together, not bolted together.
Generations
Two chips, one organizing principle
Each Obsidian generation is a research vehicle for a specific question about how physics and computation can co-design.
Obsidian 2.0 — Curvature-native silicon
A foundry-process generation whose layout and analog blocks are designed around the geometric primitives our cognitive substrate uses. Tapeout closed; the controller block is GDS-clean.
Analog and digital blocks
Where each block actually is.
Every block is reported as closed, in iter, or study. There is no “done” category — only states that can be verified.
closed
Bandgap reference
IP-clean across corners
closed
PTAT reference
SPICE-verified across temp + supply
closed
Control top block
101k cells · DRC 0 · LVS clean
in iter
PTAT layout
Routing iteration on Run 12
study
Sense amplifier
Topology study underway
closed
Security drop-in
TPM, secmem, BCH, Shamir, audit log shipped
Tapeout history
How Obsidian got to silicon
- 01
Year 1
Thermal-ratchet emulator working
Obsidian 1.0 reaches a functional emulator with the full developmental stack on top, including the production-side test harness.
- 02
Year 2
Analog block bring-up
Bandgap reference closed as IP. PTAT reference verified in SPICE. Sense-amp and PTAT layout in active iteration.
- 03
Year 2
Security drop-in complete
Hardware-security sprint shipped: TPM, secure memory, sealed storage, BCH, Shamir, audit log, lockout, and a wallet-backed post-quantum signing surface. RTL skeleton and analog NTT study landed.
- 04
Year 3
Controller GDS closed
The phase-6.A2 control top-level block closed on a foundry process. 101k cells, zero DRC, LVS clean. Final stub override applied where needed.
Measured
Where the silicon is
101k
Cells in the closed control block
Phase-6.A2 cns_ctrl_top GDS, foundry process.
0
DRC errors
LVS clean on the same run.
2,437
Tests passing on the software stack
Software and verification stack on top of the silicon program.
What Obsidian is for
Substrate-aligned silicon, in use
Cognition workloads, native
Workloads built on Stamen and Heddle run on silicon whose layout shares their organizing primitives, so locality and energy budgets are aligned end-to-end.
Hardware root of trust
The security drop-in provides a TPM, sealed storage, lockout, and PKCS#11 ML-DSA signing inside the chip. Attestation and audit are not retrofitted.
A physical platform for substrate research
Each generation is also a research vehicle. New cognitive primitives can be tried against actual silicon, not just simulators.
Related research
The work behind Obsidian.
Available through